1. Field of the Invention
The present invention relates to a DLL (Delay Locked Loop) circuit using a delay line circuit which can change a delay amount, and a test method thereof.
2. Description of the Related Art
A DLL circuit has a delay line circuit which can change a delay amount, and is a circuit which can output a signal having an arbitrary phase difference from an input signal by controlling a delay time provided to the input signal. Such semiconductor devices as an SDRAM (Synchronous Dynamic Random Access Memory) and a CPU (Central Processing Unit) operate based on the reference clock signal supplied from outside the device. As operation of such semiconductor devices becomes faster and the circuit scale thereof increases, it is becoming critical to insure phase synchronization between the internal clock signals used inside the device and the reference clock signal. The DLL circuit is used to supply an internal clock signal, of which phase synchronizes with the reference clock signal or an internal clock signal which has an arbitrary phase difference from the reference clock signal, to these semiconductor devices.
FIG. 4 shows the configuration of the DLL circuit disclosed in Japanese Unexamined Patent Application Publication No. H08-167890 (Kobayashi et al.). The DLL circuit 50 in FIG. 4 has a delay line circuit 51 for inputting a reference clock C which is supplied from the outside and providing a delay to it. The output signal C1 of the delay line circuit 51 is input to a phase comparator 52 via an internal circuit 54. The phase comparator 52 compares phases between the reference clock C and a signal C2 which is input from the internal circuit 54, and outputs a signal to indicate the phase difference to a loop filter 53. Specifically the phase comparator 52 outputs the phase difference components between the reference clock C and the signal C2 as a pulse type phase difference signal. The loop filter 53 is comprised of a charge pump and a low pass filter, and converts the phase difference signal which is input from the phase comparator 52 into analog quantity, filters out high frequency components of the phase difference signal, and then outputs it to the control terminal of the delay line circuit 51. In other words, the loop filter 53 operates as a control circuit for controlling the delay time of the delay line circuit 51. By this configuration, the delay amount of the delay line circuit 51 is adjusted so that the phases of the reference clock C and the signal C2 match, and the output signal C1 of the delay line 51 is locked to a signal having a phase difference from the reference clock C by the amount of the delay time of the internal circuit 54.
The frequency range of the reference clock signal, of which phase can be adjusted by a DLL circuit, is specified by the maximum delay time and the minimum delay time of a delay line circuit. Therefore in a DLL circuit which is optimized for high-speed operation (e.g. 400 MHz), if a test device used for a burn-in test for LSI evaluation can generate only low frequency test clock signal, the delay amount to be provided to the test clock signal exceeds the delay amount that the delay line circuit can generate, so a test cannot be performed in a state where the DLL circuit is operating normally.
To handle this problem, the DLL circuit 50 disclosed in Kobayashi et al. has a selector 55 which can select an input destination for the delay line circuit 51. To operate the DLL circuit normally, the reference clock signal C is input to the phase comparator 52 and the delay line circuit 51. When the DLL circuit 50 is tested, the reference clock signal C is input to the phase comparator 52, and a test clock signal Ctest having a phase difference from the reference clock signal C is input to the delay line circuit 51.
By this configuration, even in the case when the clock period of the reference clock signal C is long and the delay amount to be provided to the reference clock signal C cannot be generated by the delay line circuit 51, as the arrow P1 in FIG. 5 shows, the DLL circuit 50 can perform low speed operation by inputting the test clock signal Ctest of which phase is adjusted so as to be a delay amount which the delay line circuit 51 can generate. Because of this, the DLL circuit 50 can be tested with a low clock frequency.
As described above, the DLL circuit 50 disclosed in Kobayashi et al., an operation test of the delay line circuit 51 can be performed using the test clock signal of which frequency is lower than the reference clock signal during normal operation. However it has now been discovered that two lines of clock signals for testing of which phase difference is adjusted well must be input the DLL circuit 50 at testing. In order to enable a test using two lines of clock signals, the clock skew in the chip, on which the test device and the DLL circuit are mounted, must be adjusted so that the two lines of clock signals are input to the phase comparator 52 and the delay line circuit 51 with a predetermined phase difference. This causes an increase in burden in the accuracy of the test device, and in the layout design of the chip on which the DLL circuit is mounted.